Incorporating Yield Enhancement into the Floorplanning Process
IEEE Transactions on Computers
Should Yield be a Design Objective?
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
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Until recently, VLSI designers rarely considered yield issues when selecting a floorplan for a newly designed chip. This paper demonstrates that for large area VLSI chips, especially those that incorporate some fault tolerance, changes in the floorplan can affect the projected yield. We study several general floorplan structures, make some specific recommendations, and apply them to actual VLSI chips. We conclude that the floorplan of a chip can affect its projected yield in a nonnegligible way, for chips with or without fault-tolerance.