Test Pattern Generation for Realistic Bridge Faults in CMOS ICs
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Yield model for fault clusters within integrated circuits
IBM Journal of Research and Development
Computational Aspects of VLSI
DAC '94 Proceedings of the 31st annual Design Automation Conference
A unified approach to the extraction of realistic multiple bridging and break faults
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Journal of Electronic Testing: Theory and Applications
Layout compaction for yield optimization via critical area minimization
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Yield modeling and BEOL fundamentals
Proceedings of the 2001 international workshop on System-level interconnect prediction
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A stochastic-based efficient critical area extractor on OpenAccess platform
Proceedings of the 19th ACM Great Lakes symposium on VLSI
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