A comprehensive fault macromodel for opamps
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A net-oriented method for realistic fault analysis
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Low-Noise Electronic System Design
Low-Noise Electronic System Design
Analogue Fault Simulation Based on Layout-Dependent Fault Models
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Fault Modeling for the Testing of Mixed Integrated Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Hierarchy Based Statistical Fault Simulation of Mixed-Signal ICs
Proceedings of the IEEE International Test Conference on Test and Design Validity
Defect-oriented test methodology for complex mixed-signal circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
EDTC '95 Proceedings of the 1995 European conference on Design and Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal testing of VLSI analog circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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It is important to predict noise at the early stages of a top down design. In this paper, we propose a methodology to model phase noise or jitter, a key specification for phase-locked loops, using a mixed-signal hardware description language, and to simulate the effects of catastrophic faults on the phase jitter at the behavioral level. In contrast to existing approaches which either require dedicated noise simulators or postpone noise and fault simulation to the transistor level, we have successfully demonstrated that noise in a voltage-controlled oscillator, power supply noise, and their effects on the overall phase jitter within a faulty phase locked loop can be modeled and simulated earlier on at the behavioral level. Our simulation results are consistent with experimentally verified, theoretical predictions.