Modelling of hot-carrier degradation and its application for analog design for reliability
Microelectronics Journal
Validation of simulated integrated circuit reliability in conjunction with field data
Proceedings of the 2011 Grand Challenges on Modeling and Simulation Conference
On the Simulation of HCI-Induced Variations of IC Timings at High Level
Journal of Electronic Testing: Theory and Applications
WiT: optimal wiring topology for electromigration avoidance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accurate current estimation for interconnect reliability analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An approach for lifetime reliability analysis using theorem proving
Journal of Computer and System Sciences
| Hi-index | 0.03 |
Berkeley reliability tools (BERT) simulates the circuit degradation (drift) due to hot-electron degradation in MOSFETs and bipolar transistors and predicts circuit failure rates due to oxide breakdown and electromigration in CMOS, bipolar, and BiCMOS circuits. With the increasing importance of reliability in today's and future technology, a reliability simulator such as this is expected to serve as the engine of design-for-reliability in a building-in-reliability paradigm. BERT works in conjunction with a circuit simulator such as SPICE in order to simulate reliability for actual circuits, and, like SPICE, acts as an interactive tool for design. BERT is introduced and the current work being done is summarized. BERT is used to study the reliability of a BiCMOS inverter chain, and performance data are presented