Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
ArchC: A SystemC-Based Architecture Description Language
SBAC-PAD '04 Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing
A simulation methodology for reliability analysis in multi-core SoCs
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
A Framework for Architecture-Level Lifetime Reliability Modeling
DSN '07 Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks
Elimination of Overhead Operations in Complex Loop Structures for Embedded Microprocessors
IEEE Transactions on Computers
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Statistical reliability analysis under process variation and aging effects
Proceedings of the 46th Annual Design Automation Conference
AgeSim: a simulation framework for evaluating the lifetime reliability of processor-based SoCs
Proceedings of the Conference on Design, Automation and Test in Europe
SESAM: An MPSoC Simulation Environment for Dynamic Application Processing
CIT '10 Proceedings of the 2010 10th IEEE International Conference on Computer and Information Technology
Towards a parameterizable cycle-accurate ISS in ArchC
AICCSA '10 Proceedings of the ACS/IEEE International Conference on Computer Systems and Applications - AICCSA 2010
Aging analysis at gate and macro cell level
Proceedings of the International Conference on Computer-Aided Design
Berkeley reliability tools-BERT
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A novel four-step search algorithm for fast block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
Relation between HCI-induced performance degradation and applications in a RISC processor
IOLTS '12 Proceedings of the 2012 IEEE 18th International On-Line Testing Symposium (IOLTS 2012)
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Die shrinking combined with the non-ideal scaling of voltage increases the probability of MOS transistors to encounter HCI. This mechanism causes timing degradation and possibly failures in ICs. The evaluation of timing degradation early in the design flow becomes a must-have to ensure the expected time-to-market and IC lifetime. In this paper, we propose a framework for simulating and analyzing the HCI-induced timing variations at high abstraction level. We first present a bottom-up approach to move information about timing degradation up to the higher abstraction layers. Then, we describe a simulation framework for analyzing the HCI-induced timing variations, and we evaluate its performance and accuracy. Finally, by considering a sample processor, we analyze the impact of the instruction set architecture on slack times and critical paths.