DIVA: a reliable substrate for deep submicron microarchitecture design
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
A survey of design techniques for system-level dynamic power management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Design issues for dynamic voltage scaling
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Dynamic Power Management: Design Techniques and CAD Tools
Dynamic Power Management: Design Techniques and CAD Tools
Hardware-software cosynthesis of multi-mode multi-task embedded systems with real-time constraints
Proceedings of the tenth international symposium on Hardware/software codesign
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Dynamic Thermal Management for High-Performance Microprocessors
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
The Case for Lifetime Reliability-Aware Microprocessors
Proceedings of the 31st annual international symposium on Computer architecture
Exploiting Structural Duplication for Lifetime Reliability Enhancement
Proceedings of the 32nd annual international symposium on Computer Architecture
Fault-Tolerant Systems
A Framework for Architecture-Level Lifetime Reliability Modeling
DSN '07 Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks
Power and reliability management of SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On Modeling the Lifetime Reliability of Homogeneous Manycore Systems
PRDC '08 Proceedings of the 2008 14th IEEE Pacific Rim International Symposium on Dependable Computing
High-Speed VLSI Interconnections
High-Speed VLSI Interconnections
Multi-mechanism reliability modeling and management in dynamic systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Lifetime reliability-aware task allocation and scheduling for MPSoC platforms
Proceedings of the Conference on Design, Automation and Test in Europe
Customer-aware task allocation and scheduling for multi-mode MPSoCs
Proceedings of the 48th Design Automation Conference
Mapping of applications to MPSoCs
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
On the Simulation of HCI-Induced Variations of IC Timings at High Level
Journal of Electronic Testing: Theory and Applications
Proceedings of the Conference on Design, Automation and Test in Europe
Cost-effective lifetime and yield optimization for NoC-based MPSoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Use it or lose it: wear-out and lifetime in future chip multiprocessors
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
A low-cost fault tolerant solution targeting commercial FPGA devices
Journal of Systems Architecture: the EUROMICRO Journal
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Aggressive technology scaling has an ever-increasing adverse impact on the lifetime reliability of microprocessors. This paper proposes a novel simulation framework for evaluating the lifetime reliability of processor-based system-on-a-chips (SoCs), namely AgeSim, which facilitates designers to make design decisions that affect SoCs' mean time to failure. Unlike existing work, AgeSim can simulate failure mechanisms with arbitrary lifetime distributions and do not require to trace the system's reliability-related factors over its entire lifetime, and hence is more efficient and accurate. Two case studies are conducted to show the flexibility and effectiveness of the proposed methodology.