A practical approach to static signal electromigration analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
A current driven routing and verification methodology for analog applications
Proceedings of the 37th Annual Design Automation Conference
Coupled analysis of electromigration reliability and performance in ULSI signal nets
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Interconnect lifetime prediction under dynamic stress for reliability-aware design
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A study of Through-Silicon-Via impact on the 3D stacked IC layout
Proceedings of the 2009 International Conference on Computer-Aided Design
Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles
Proceedings of the 19th international symposium on Physical design
Uniting to overcome a mounting BEOL electromigration reliability challenge
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
Global routing based on Steiner min-max trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Static electromigration analysis for on-chip signal interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Electromigration (EM) has become a key reliability concern for nanometer IC designs. For 3D ICs, higher current density/temperature and TSV-induced thermal mechanical stress further exacerbate the EM issue compared to 2D ICs. In this paper, we analyze the root causes of EM for 3D IC signal nets, with consideration of current density, temperature, and TSV-induced thermal mechanical stress. We develop compact EM models for both DC and AC signal nets using detailed finite-element-analysis (FEA) and build EM library for meantime-to-failure (MTTF). For AC signal nets, we convert AC current into equivalent DC current and model EM with it. One unique property of EM in 3D ICs is that, depending on the current direction, TSV-induced stress may degrade or improve the MTTF, thus routing plays an important role for EM mitigation. We suggest EM-aware routing algorithms for 3D ICs for the first time to our best knowledge, guided by our stress-aware EM modeling. Experimental result shows that our proposed approach improves EM-robustness of 3D IC benchmarks significantly, e.g., 66.4% less EM-violated grids with little sacrifice of conventional routing objectives.