Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Thermal and Power Integrity Based Power/Ground Networks Optimization
Proceedings of the conference on Design, automation and test in Europe - Volume 2
The Case for Lifetime Reliability-Aware Microprocessors
Proceedings of the 31st annual international symposium on Computer architecture
A temperature-aware simulation environment for reliable ULSI chip design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
3-D Thermal-ADI: a linear-time chip level transient thermal simulator
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The need for a full-chip and package thermal model for thermally optimized IC designs
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Electrothermal analysis and optimization techniques for nanoscale integrated circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
TAPHS: thermal-aware unified physical-level and high-level synthesis
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Exploring "temperature-aware" design in low-power MPSoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Adaptive chip-package thermal analysis for synthesis and design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Reliability modeling and management in dynamic microprocessor-based systems
Proceedings of the 43rd annual Design Automation Conference
ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon
IEEE Design & Test
Interconnect lifetime prediction for reliability-aware systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reliability-aware design for nanometer-scale devices
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Credit-based dynamic reliability management using online wearout detection
Proceedings of the 5th conference on Computing frontiers
Multi-mechanism reliability modeling and management in dynamic systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Process variation and temperature-aware reliability management
Proceedings of the Conference on Design, Automation and Test in Europe
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Electromigration-aware routing for 3D ICs with stress-aware EM modeling
Proceedings of the International Conference on Computer-Aided Design
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Thermal effects are becoming a limiting factor in high-performance circuit design due to the strong temperature-dependence of leakage power, circuit performance, IC package cost and reliability. While many interconnect reliability models assume a constant temperature, this paper presents a physics-based model for estimating interconnect lifetime for any time-varying temperature/current profile. This model is verified with numerical solutions. With this model, we show that designers may be more aggressive with the temperature profiles that are allowed on a chip. In fact, our model reveals that when the temperature magnitude variation is small, average temperature (instead of worst-case temperature) can be used to accurately predict interconnect lifetime, allowing for significant design margin reclamation in reliability-aware design. Even when the variation of temperature magnitude is large, our model shows that using the maximum temperature is still too conservative for interconnect lifetime prediction. Therefore, our model not only increases the accuracy of reliability estimates, but also enables designers to consider more aggressive designs. This model is similarly useful for temperature-aware dynamic runtime management.