The Elmore delay as bound for RC trees with generalized input signals

Transmission line synthesis

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

A sequential quadratic programming approach to concurrent gate and wire sizing

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Coping with RC(L) interconnect design headaches

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

An explicit RC-circuit delay approximation based on the first three moments of the impulse response

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Analytical delay models for VLSI interconnects under ramp input

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Selection of Voltage Thresholds for Delay Measurement

Analog Integrated Circuits and Signal Processing - Special issue: analog design issues in digital VSLI circuits and systems

Interconnect design for deep submicron ICs

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

An exact solution to simultaneous technology mapping and linear placement problem

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Timing metrics for physical design of deep submicron technologies

ISPD '98 Proceedings of the 1998 international symposium on Physical design

Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model

ISPD '99 Proceedings of the 1999 international symposium on Physical design

FAR-DS: full-plane AWE routing with driver sizing

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Buffer insertion with accurate gate and interconnect delay computation

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Maze routing with buffer insertion and wiresizing

Proceedings of the 37th Annual Design Automation Conference

Predicting coupled noise in RC circuits by matching 1, 2, and 3 moments

Proceedings of the 37th Annual Design Automation Conference

RLC interconnect delay estimation via moments of amplitude and phase response

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Predicting coupled noise in RC circuits

DATE '00 Proceedings of the conference on Design, automation and test in Europe

Memory-efficient interconnect optimization

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Delay Models for MCM Interconnects when Response is Non-Monotone

MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference

An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

An efficient hierarchical timing-driven Steiner tree algorithm for global routing

Integration, the VLSI Journal

Fitted Elmore delay: a simple and accurate interconnect delay model

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Efficient decoupling capacitor planning via convex programming methods

Proceedings of the 2006 international symposium on Physical design

Statistical based link insertion for robust clock network design

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Minimum decoupling capacitor insertion in VLSI power/ground supply networks by semidefinite and linear programs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Discharge-path-based antenna effect detection and fixing for X-architecture clock tree

Integration, the VLSI Journal

An efficient delay metric on RC interconnects under saturated ramp inputs

ICCSA'06 Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part IV