Signal degradation through module pins in VLSI packaging
IBM Journal of Research and Development
AWESpice: a general tool for the accurate and efficient simulation of interconnect problems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Transient simulation of lossy interconnect
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
RICE: Rapid interconnect circuit evaluator
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Efficient transient simulation of lossy interconnect
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Fast approximation of the transient response of Lossy Transmision Line Trees
DAC '93 Proceedings of the 30th international Design Automation Conference
A simplified synthesis of transmission lines with a tree structure
Analog Integrated Circuits and Signal Processing - Special issue on high-speed interconnects
The Elmore delay as bound for RC trees with generalized input signals
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An explicit RC-circuit delay approximation based on the first three moments of the impulse response
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Analytical delay models for VLSI interconnects under ramp input
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Best Approximation Method: An Introduction
Best Approximation Method: An Introduction
Wire-sizing for delay minimization and ringing control using transmission line model
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A graph based algorithm for optimal buffer insertion under accurate delay models
Proceedings of the conference on Design, automation and test in Europe
Reducing bus delay in submicron technology using coding
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A construction of minimal delay Steiner tree using two-pole delay model
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A fast and accurate delay estimation method for buffered interconnects
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
An improved Elmore delay model for VLSI interconnects
Mathematical and Computer Modelling: An International Journal
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Elmore delay has been extensively used for interconnect delay estimation because its simplicity of evaluation makes it appropriate for layout design. However, since Elmore delay does not take into account the effect of inductance, the discrepancy between actual delay and Elmore delay becomes significant for long RLC transmission lines, such as for MCM and PCB interconnects. We describe a simple two-pole based analytic delay model that estimates arbitrary threshold delays for RLC lines when the response is nonmonotone; our model is far more accurate than the Elmore model. We also describe an application of our model for controlling response undershoot/overshoot and for the reduction of interconnect delay through constraints on the moments.