Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A design for testability scheme with applications to data path synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A data path synthesis method for self-testable designs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments
DAC '93 Proceedings of the 30th international Design Automation Conference
Microarchitectural synthesis of VLSI designs with high test concurrency
DAC '94 Proceedings of the 31st annual Design Automation Conference
Incorporating testability considerations in high-level synthesis
Journal of Electronic Testing: Theory and Applications
Data path allocation for synthesizing RTL design with low BIST area overhead
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
High-level synthesis for testability: a survey and perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An improved method for RTL synthesis with testability tradeoffs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
SYNCBIST: SYNthesis for Concurrent Built-In-Self-Testability
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Test Synthesis in the Behavioral Domain
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Design for Testability Using Architectural Descriptions
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Transforming Behavioral Specifications to Facilitate Synthesis of Testable Designs
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
BIST Testability Enhancement of System Level Circuits: Experience with An Industrial Design
ATS '96 Proceedings of the 5th Asian Test Symposium
Testability metrics for synthesis of self-testable designs and effective test plans
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Behavioral-structural testability modeling and synthesis for bist with applications to high-level synthesis
A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis
Journal of Electronic Testing: Theory and Applications
A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis
ETW '00 Proceedings of the IEEE European Test Workshop
BISTing Data Paths at Behavioral Level
ITC '00 Proceedings of the 2000 IEEE International Test Conference
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High-Level Test Synthesis (HLTS), a term introduced in recent years, promises automatic enhancement of testability of a circuit. In this paper we will show how HLTS can achieve higher testability for BIST-oriented test methodologies. Our results show considering testability during high-level synthesis, better testability can be obtained when compared to DFT at low level. Transformation for testability, which allows behavioral modification for testability, is a very powerful HLTS technique.