Lower bounds on test resources for scheduled data flow graphs
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Allocation Techniques for Reducing BIST Area Overhead ofData Paths
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
High-Level Test Synthesis for Behavioral and Structural Designs
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Estimation of BIST Resources During High-Level Synthesis
Journal of Electronic Testing: Theory and Applications
BISTing Data Paths at Behavioral Level
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Concurrent BIST synthesis and test scheduling using genetic algorithms
International Journal of Computers and Applications
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