Logic testing and design for testability
Logic testing and design for testability
Statecharts: A visual formalism for complex systems
Science of Computer Programming
A data path synthesis method for self-testable designs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
High-level synthesis for testability: a survey and perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Symbolic optimization of FSM networks based on sequential ATPG techniques
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Behavioral synthesis for easy testability in data path scheduling
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A Classification of CASE Technology
Computer
Design for Testability in Hardware-Software Systems
IEEE Design & Test
Scheduling for Reactive Real-Time Systems
IEEE Micro
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A high-level synthesis approach to design of fault-tolerant systems
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Partitioning of Hardware-Software Embedded Systems: A Metrics-based Approach
Integrated Computer-Aided Engineering
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Hardware-software codesign is emerging as a global top-down solution to design of reactive embedded systems, starting from high level specifications and going - through hardware-software partitioning and cosynthesis - to link with lower level CAD and CASE tools. At the top level, requirements usually take into account cost and time bounds; we propose here to insert at the same level (i.e., before hardware{software partitioning) also testability requirements, so as to grant the possibility of checking correct interaction between the specified objects whatever their subsequent implementation. A formalism for definition of interfaces and protocols is presented; rules aimed at verification of the interface syntax are introduced.