Concurrent error detection at architectural level
Proceedings of the 11th international symposium on System synthesis
Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors
IEEE Transactions on Computers
Semiconcurrent Error Detection in Data Paths
IEEE Transactions on Computers
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An innovative approach for high-level synthesis of digital circuits with semi-concurrent self-checking abilities is introduced, achieving a compromise between redundancy and checking effectiveness. Attention is mainly focused on the data path, described as a general Sequencing Graph including linear paths as well as loops and branches. A reference architecture is defined; a technique allowing to reduce redundancy through resource sharing is then introduced, leading to synthesis of the self-checking architecture. An algorithm is proposed to simultaneously schedule and allocate the resources, while keeping error aliasing as reduced as possible. The desired checking periodicity is guarantee by the algorithm.