Design of VHDL-based totally self-checking finite-state machine and data-path descriptions

Authors:
C. Bolchini;R. Montandon;F. Salice;D. Sciuto
Affiliations:
Politecnico di Milano, Milan, Italy;Politecnico di Milano, Milan, Italy;Politecnico di Milano, Milan, Italy;Politecnico di Milano, Milan, Italy
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2000

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Abstract

This paper presents a complete methodology to design a totally self-checking (TSC) sequential system based on the generic architecture of finite-state machine and data path (FSMD), such as the one deriving from VHDL specifications. The control part of the system is designed to be self-checking by adopting a state assignment providing a constant Hamming distance between each pair of binary codes. The design of the data path is based on both classical methodologies (e.g., parity, Berger code) and ad hoc strategies (e.g., multiplexer cycle) suited for the specific circuit structure. Self-checking properties and costs are evaluated on a set of benchmark FSM's and on a number of VHDL circuits.