Design of VHDL-based totally self-checking finite-state machine and data-path descriptions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Digital Design: Principles and Practices
Digital Design: Principles and Practices
The Designer's Guide to VHDL
Self-Checking of FPGA-Based Control Units
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Finite State Machine Synthesis with Concurrent Error Detection
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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This paper presents a self-correcting control unit design using Hamming codes for finite state machine (FSM) state encoding. The adopted technique can correct single-bit errors and detect two-bit errors in the FSM register within the same clock cycle. The main contribution is the development of a parameterizable VHDL package and the respective error-correcting modules, which can easily be added to an FSM specification using any state assignment strategy and having any number of inputs, outputs and states. Besides of application to FSM error correction, the developed tools can easily be adapted to other applications where error detection and correction is required.