Introduction to VLSI Systems
Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes
IEEE Transactions on Computers
A Totally Self-Checking 1-Out-of-3 Checker
IEEE Transactions on Computers
Note on Self-Checking Checkers
IEEE Transactions on Computers
Design of Fast Self-Testing Checkers for a Class of Berger Codes
IEEE Transactions on Computers
Embedded self-testing checkers for low-cost arithmetic codes
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Technologies for designing dependable A/D converters
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
On the Design of Self-Checking Controllers with Datapath Interactions
IEEE Transactions on Computers
Design of Totally Self-Checking Checker for 1-out-of-3 Code
IEEE Transactions on Computers
A fault-tolerant permutation network modulo arithmetic processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 14.99 |
A new design for a totally self-checking 1-out-of-n checker is presented. A comparison with other existing methods [1], [10] is given. It is shown that for many practical values of n the new scheme requires less hardware and/or is faster than the other methods. The entire checker can be tested by applying all of the n possible 1-out-of-n inputs.