A self-checking generalized prediction checker and its use for built-in testing
IEEE Transactions on Computers
Efficient Design of Totally Self-Checking Checkers for all Low-Cost Arithmetic Codes
IEEE Transactions on Computers
Error-control coding for computer systems
Error-control coding for computer systems
Design and performance of the IBM Enterprise System/900 Type 9121 Vector Facility
IBM Journal of Research and Development
Accumulator-Based Compaction of Test Responses
IEEE Transactions on Computers
On the effectiveness of residue code checking for parallel two's complement multipliers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal Self-Testing Embedded Parity Checkers
IEEE Transactions on Computers
Embedded Totally Self-Checking Checkers: A Practical Design
IEEE Design & Test
Self-Checking Comparator with One Periodic Output
IEEE Transactions on Computers
Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Test response compaction using arithmetic functions
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Comment on the Sequential and Indeterminate Behavior of an End-Around-Carry Adder
IEEE Transactions on Computers
Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes
IEEE Transactions on Computers
Detection of Storage Errors in Mass Memories Using Low-Cost Arithmetic Error Codes
IEEE Transactions on Computers
Strongly Fault Secure Logic Networks
IEEE Transactions on Computers
Design and Application of Self-Testing Comparators Implemented with MOS PLA's
IEEE Transactions on Computers
Totally Self-Checking Checker for 1-out-of-n Code Using Two-Rail Codes
IEEE Transactions on Computers
On Totally Self-Checking Checkers for Separable Codes
IEEE Transactions on Computers
Arithmetic Error Codes: Cost and Effectiveness Studies for Application in Digital System Design
IEEE Transactions on Computers
Self-Testing Embedded Parity Checkers
IEEE Transactions on Computers
Embedded Checker Architectures for Cyclic and Low-Cost Arithmetic Codes
Journal of Electronic Testing: Theory and Applications
Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Codes
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
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In highly reliable systems, error detecting codes are employed and errors caused by faultyhardware are indicated on-line by code checkers. Wepresent two novel architectures of embedded self-testingcheckers for low-cost arithmetic codes, one based oncode word generators and adders, the other based oncode word accumulators. In these schemes, the codechecker receives all possible code words but one, irrespective of the number of different code words that areproduced by the circuit under check (CUC). So anycode checker can be employed that is self-testing forall or a particular subset of code words, and the structure of the code checker need not be tailored to the setof code words produced by the CUC. The proposed codeword generators and accumulators are built from simple standard hardware structures, counters and end-around-carry adders. They can also be utilized in anoff-line BIST environment as pattern generators andtest response compactors.