Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Introduction to algorithms
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Design Issues in Division and Other Floating-Point Operations
IEEE Transactions on Computers
Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications
Algebric Decision Diagrams and Their Applications
Formal Methods in System Design
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Telescopic units: a new paradigm for performance optimization of VLSI designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Energy-efficient datapath scheduling using multiple voltages and dynamic clocking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ILP models for simultaneous energy and transient power minimization during behavioral synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Synthesis of synchronous elastic architectures
Proceedings of the 43rd annual Design Automation Conference
An efficient mechanism for performance optimization of variable-latency designs
Proceedings of the 44th annual Design Automation Conference
Speculation in elastic systems
Proceedings of the 46th Annual Design Automation Conference
Timing-driven optimization using lookahead logic circuits
Proceedings of the 46th Annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Masking timing errors on speed-paths in logic circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Variable-latency design by function speculation
Proceedings of the Conference on Design, Automation and Test in Europe
Microarchitectural Transformations Using Elasticity
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A clock control strategy for peak power and RMS current reduction using path clustering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 14.98 |
In high-performance systems, variable-latency units are often employed to improve the average throughput when the worst-case delay exceeds the cycle time. Traditionally, units of this type have been hand-designed. In this paper, we propose a technique for the automatic synthesis of variable-latency units that is applicable to large data-path modules. We define and study an optimization problem, timed supersetting, whose solution is at the kernel of the procedure for automatic generation of variable-latency units. We contribute a new algorithm for solving timed supersetting in the most difficult case, that is, when the timing behavior of the circuit is expressed through an accurate delay model. The proposed solution overcomes the computational limitations of previous approaches and its robustness is experimentally demonstrated by obtaining high-throughput, variable-latency implementations for all the largest circuits in the Iscas '85 and Iscas '89 benchmark suites, as well as for some realistic, high-performance arithmetic units.