Incremental high-level synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
High-level synthesis with distributed controller for fast timing closure
Proceedings of the International Conference on Computer-Aided Design
A metric for layout-friendly microarchitecture optimization in high-level synthesis
Proceedings of the 49th Annual Design Automation Conference
Fast and effective placement and routing directed high-level synthesis for FPGAs
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
Critical-path-aware high-level synthesis with distributed controller for fast timing closure
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Achieving design closure is one of the biggest challenges for modern very large-scale integration system designers. This problem is exacerbated by the lack of high-level design-automation tools that consider the increasingly important impact of physical features, such as interconnect, on integrated circuit area, performance, and power consumption. Using physical information to guide decisions in the behavioral-level stage of system design is essential to solve this problem. In this paper, we present an incremental floorplanning high-level-synthesis system. This system integrates high-level and physical-design algorithms to concurrently improve a design's schedule, resource binding, and floorplan, thereby allowing the incremental exploration of the combined behavioral-level and physical-level design space. Compared with previous approaches that repeatedly call loosely coupled floorplanners for physical estimation, this approach has the benefits of efficiency, stability, and better quality of results. The average CPU time speedup resulting from unifying incremental physical-level and high-level synthesis is 24.72times and area improvement is 13.76%. The low power consumption of a state-of-the-art low-power interconnect-aware high-level-synthesis algorithm is maintained. The benefits of concurrent behavioral-level and physical-design optimization increased for larger problem instances.