Two-Phase Asynchronous Pipeline Control

Authors:
S. S. Appleton;S. V. Morton;M. J. Liebelt
Affiliations:
-;-;-
Venue:
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Year:
1997

Citing 0
Cited 3

Practical advances in asynchronous design and in asynchronous/synchronous interfaces

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
A behavioral synthesis system for asynchronous circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

In this paper the potential speed and power efficiency of two-phase asynchronous systems operating under a bounded-delay model are explored. It is shown that two-phase bounded-delay systems can significantly outperform four-phase approaches published to date. The design of a prototype microprocessor using this two-phase approach is then described, and preliminary results are presented.