Communications of the ACM
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The design of an asynchronous VHDL synthesizer
Proceedings of the conference on Design, automation and test in Europe
Dynamic Logic in Four-Phase Micropipelines
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
A behavioral synthesis system for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verification of delay insensitivity in bit-level pipelined dual-rail threshold logic adders
EHAC'08 Proceedings of the 7th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Algebraic model for the intercommunicating hardware components behaviour
ICCOMP'08 Proceedings of the 12th WSEAS international conference on Computers
The design of an asynchronous blocksorter
ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing
A VHDL-based design methodology for asynchronous circuits
WSEAS Transactions on Circuits and Systems
The design of a simple asynchronous processor
MMACTEE'10 Proceedings of the 12th WSEAS international conference on Mathematical methods and computational techniques in electrical engineering
The design of sharing resources for asynchronous systems
MMACTEE'10 Proceedings of the 12th WSEAS international conference on Mathematical methods and computational techniques in electrical engineering
Synchronous design flow for globally asynchronous locally synchronous systems
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
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The asynchronous circuit style is based on micropipelines, a style used to develop asynchronous microprocessors at Manchester University. This paper has presented some engineering work on developing a technique of sharing resources for micropipeline circuits. The work presented in this paper shows a comparison of 2-phase and 4-phase implementations in transistor count, speed, and energy. Though the nature of the work is mainly engineering, there are some significant new insights gained in the course of the work. In resource sharing the 2-phase implementations have better performance than the four-phase implementations. There is no "return to zero" problem. Fork and join cost nothing to the two-phase implementations. With some additional buffer stages the 4-phase implementations using the fully decoupled and long hold latch control circuits can also implement resource sharing. However, the four-phase implementations using the simple and semi-decoupled latch control circuits require more buffer stages to avoid deadlock.