A behavioral synthesis system for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Custom floating-point unit generation for embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Traditionally, the data processed by a synthesized digital design is fixed (occasionally variable) width integer, and the functional units available are concomitantly simple ladders, subtractors, multipliers, multiplexers, and so on). The aims of paper work are two-fold: 1) to provide a library of high-level floating-point functions (trigonometric, transcendental, complex) to support the synthesis of behavioral designs incorporating complicated sets of floating-point operations and 2) to incorporate this into an optimizing behavioral synthesis environment. Floating-point units are large and cumbersome and an optimization technique that allows the internal substructures of these units to be shared (in both space and time) produces a dramatic decrease in the overall hardware resources required to support a design. The floating-point modules themselves are each implemented in several ways: as an iterative series, by table lookup, and using the coordinate rotation digital computer algorithm. The choice of implementation is left to the optimizer, which makes individual binding choices based on global knowledge of the overall design. This paper describes the library and the optimization algorithm and demonstrates the overall system use with an exemplar: a floating-point quadratic equation solver capable of delivering complex roots, realized using 30% of a Xilinx 40125XV field-programmable gate array