Practical advances in asynchronous design and in asynchronous/synchronous interfaces
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A behavioral synthesis system for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Loop pipelining for high-throughput stream computation using self-timed rings
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
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This paper describes the design and verification of a high-performance asynchronous differential equation solver benchmark circuit. The design has low-control-overhead which allows its average-case speed (tested at 22/spl deg/C and 3.3 V) to be 48% faster than any comparable synchronous design (designed to operate at 100/spl deg/C and 3 V for the slow process corner). The techniques to reduce completion sensing overhead and hide control overhead at the circuit, architectural, and protocol levels are discussed. In addition, symbolic model checking techniques are described that were used to gain higher confidence in the correctness of the timed distributed control.