The design of a high-performance cache controller: a case study in asynchronous synthesis
Integration, the VLSI Journal - Special issue on asynchronous systems
The Post Office experience: designing a large asynchronous chip
Integration, the VLSI Journal - Special issue on asynchronous systems
Designing an Asynchronous Communications Chip
IEEE Design & Test
Basic gate implementation of speed-independent circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Synthesis of asynchronous systems targeting finite state machines
Synthesis of asynchronous systems targeting finite state machines
A technique for synthesizing distributed burst-mode circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Synthesis of hazard-free customized CMOS complex-gate networks under multiple-input changes
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Computer-aided synthesis and verification of gate-level timed circuits
Computer-aided synthesis and verification of gate-level timed circuits
Automatic synthesis of extended burst-mode circuits using generalized C-elements
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Synthesis of Hazard-Free Asynchronous Circuits Based on Characteristic Graph
IEEE Transactions on Computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic synthesis of 3D asynchronous state machines
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Automatic gate-level synthesis of speed-independent circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Direct synthesis of timed asynchronous circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Practical Asynchronous Controller Design
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Average-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
RAPPID: An Asynchronous Instruction Length Decoder
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Sequential optimization of asynchronous and synchronous finite-state machines: algorithms and tools
Sequential optimization of asynchronous and synchronous finite-state machines: algorithms and tools
Covering conditions and algorithms for the synthesis of speed-independent circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hazard-free implementation of speed-independent circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Structural methods for the synthesis of speed-independent circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast heuristic and exact algorithms for two-level hazard-free logic minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic synthesis of extended burst-mode circuits. II. (Automatic synthesis)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a new approach to two-level hazard-free logic minimization in the context of extended burst-mode finite state machine synthesis targeting generalized C-elements (gC). No currently available minimizers for literal-exact two-level hazard-free logic minimization of extended burst-mode gC controllers can handle large circuits without synthesis times ranging up over thousands of seconds. Even existing heuristic approaches take too much time when iterative exploration over a large design space is required and do not yield minimum results. The logic minimization approach presented in this paper is based on state graph exploration in conjunction with single-cube cover algorithms, an approach that has not been considered for minimization of extended burst-mode finite state machines previously. Our algorithm achieves very fast logic minimization by introducing compacted state graphs and cover tables and an efficient single-cube cover algorithm for single-output minimization. Our exact logic minimizer finds minimal number of literal solutions to all currently available benchmarks, in less than one second on a 333 MHz microprocessor -- more than three orders of magnitude faster than existing literal exact methods, and over an order of magnitude faster than existing heuristic methods for the largest benchmarks. This includes a benchmark that has never been possible to solve exactly in number of literals before.