Direct synthesis of timed asynchronous circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A structural encoding technique for the synthesis of asynchronous circuits
Fundamenta Informaticae - Application of concurrency to system design
Synthesis of Reactive Systems: Application to Asynchronous Circuit Design
Concurrency and Hardware Design, Advances in Petri Nets
ILP Models for the Synthesis of Asynchronous Control Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Hardware and Petri nets: application to asynchronous circuit design
ICATPN'00 Proceedings of the 21st international conference on Application and theory of petri nets
A Polynomial-Time Algorithm for Checking Consistency of Free-Choice Signal Transition Graphs
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
A structural encoding technique for the synthesis of asynchronous circuits
Fundamenta Informaticae - Application of Concurrency to System Design
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Asynchronous circuits can be modeled as concurrent systems in which events are interpreted as signal transitions. The synthesis of concurrent systems implies the analysis of a vast state space that often requires computationally expensive methods. This work presents new methods for the synthesis of speed-independent circuits from a new perspective, overcoming both the analysis and computation complexity bottlenecks. The circuits are specified by free-choice signal transition graphs (STGs), a subclass of interpreted Petri nets. The synthesis approach is divided into the following steps: correctness, binary coding, implementability conditions, and logic synthesis. Each step is efficiently implemented by applying a set of structural techniques that analyze STGs without explicitly enumerating the underlying state space. Experimental results show that circuits can be generated from specifications that exceed in several orders of magnitude the largest STGs ever synthesized-with over 1027 states. Computation times are also dramatically reduced. Nevertheless, the quality of results does not suffer from the use of structural techniques