Self-timed rings and their application to division
Self-timed rings and their application to division
CMOS design of the tree arbiter element
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Practical Design of Globally-Asynchronous Locally-Synchronous Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Asynchronous Wrapper for Heterogeneous Systems
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Modeling and Verification of Globally Asynchronous and Locally Synchronous Ring Architectures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Coherence Ordering for Ring-based Chip Multiprocessors
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Integration, the VLSI Journal
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Two-phase synchronization with sub-cycle latency
Integration, the VLSI Journal
Analysis and optimization of pausible clocking based GALS design
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
High rate data synchronization in GALS socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scalable and partitionable asynchronous arbiter for micro-threaded chip multiprocessors
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
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The lack of proven mechanisms for transferring data between multiple synchronous islands has been a major impediment for applying globally asynchronous locally synchronous (GALS) techniques to SoC design. We have implemented on a VLSI test chip three alternative solutions to fill the gap: an arbitrated bus, a switch, and a self-timed ring. Circuit details and various extensions of the basic ring structure are also being discussed. These include bypassing ring transceivers to free the local islands from managing enroute traffic and transceivers that inform the sender in case a defective receiver is unable to accept a data item. This is indispensable to prevent any deadlocks. For a ring with five nodes a total data throughput of 520 MegaDataPackets/s was achieved.