Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Automatic synthesis of burst-mode asynchronous controllers
Automatic synthesis of burst-mode asynchronous controllers
Designing an Asynchronous Communications Chip
IEEE Design & Test
Asynchronous Circuits for Low Power: A DCC Error Corrector
IEEE Design & Test
The Stanford FLASH multiprocessor
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Synthesis of asynchronous systems targeting finite state machines
Synthesis of asynchronous systems targeting finite state machines
Principles of digital design
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Synthesis of asynchronous controllers for heterogeneous systems
Synthesis of asynchronous controllers for heterogeneous systems
Design of a cell library for asynchronous microengines
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
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Asynchronous (self-timed) circuits are quite natural for realizing control-intensive designs. Many such designs are of reactive nature and inherently complex due to complicated communication protocols. In these situations programmable controllers are preferable over hardwired controllers to allow design decisions to be bound late, help correct errors that may slip through the verification process, and even permit run-time modification of control algorithms to best suit the current situation. Virtually all recent work in asynchronous controller design focusses on generating hardwired controllers. In this paper, we propose an architecture for programmable asynchronous controllers in the form of a microprogrammed asynchronous "microengine". Architectures utilizing both two-phase and four-phase handshaking are proposed. The datapath structure of the asynchronous microengine is modular and easily extensible, facilitating changes during the design phase. We ensure high performance of the asynchronous microengine by exploiting concurrency between operations and employ efficient control structures. Initial results show that the proposed microengine can yield performance close to that offered by automated high-level synthesis tools targeting custom hardwired burst-mode machines for control.