Concurrency-oriented optimization for low-power asynchronous systems
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Testing two-phase transition signaling based self-timed circuits in a synthesis environment
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
SHILPA: a high-level synthesis system for self-timed circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Self-Timed Carry-Lookahead Adders
IEEE Transactions on Computers - Special issue on computer arithmetic
The design of an asynchronous VHDL synthesizer
Proceedings of the conference on Design, automation and test in Europe
Transformations for the synthesis and optimization of asynchronous distributed control
Proceedings of the 38th annual Design Automation Conference
Specification and Validation of Control-Intensive IC's in hopCP
IEEE Transactions on Software Engineering
Fly - A Modifiable Hardware Compiler
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
DFT for fast testing of self-timed control circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
Testing self-timed circuits using partial scan
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Single-rail handshake circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Critical hazard free test generation for asynchronous circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
ACT: A DFT Tool for Self-Timed Circuits
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Automatic placement of micropipeline standard cells
WSEAS Transactions on Circuits and Systems
A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Behavioral synthesis of asynchronous circuits using syntax directed translation as backend
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Specifying and property checking the AMULET1 address interface
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
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