Communications of the ACM
The design of an asynchronous microprocessor
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Translating concurrent communicating programs into asynchronous circuits
Translating concurrent communicating programs into asynchronous circuits
Asynchronous Circuits for Low Power: A DCC Error Corrector
IEEE Design & Test
The Counterflow Pipeline Processor Architecture
IEEE Design & Test
Testing macro-module-based self-timed circuits
Testing macro-module-based self-timed circuits
Procedures for Eliminating Static and Dynamic Hazards in Test Generation
IEEE Transactions on Computers
ACT: A DFT Tool for Self-Timed Circuits
ITC '97 Proceedings of the 1997 IEEE International Test Conference
A novel automatic test pattern generator for asynchronous sequential digital circuits
Microelectronics Journal
| Hi-index | 0.00 |
We describe a technique to generate critical hazard-free tests for self-timed control circuits built using a macro-module library, in a partial scan based DFT environment. We propose a six-valued algebra to generate these tests which are guaranteed to be critical hazard free under an unbounded delay model. This algebra has been incorporated in a D-algorithm based automatic test pattern generator.