Communications of the ACM
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Testing delay-insensitive circuits
Testing delay-insensitive circuits
Translating concurrent communicating programs into asynchronous circuits
Translating concurrent communicating programs into asynchronous circuits
Using FPGAs to implement self-timed systems
Journal of VLSI Signal Processing Systems - Special issue on field-programmable gate arrays
Testing two-phase transition signaling based self-timed circuits in a synthesis environment
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
A Comparison of Self-Timed Design Using FPGA, CMOS, and GaAs Technologies
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Test Quality of Asynchronous Circuits: A Defect-oriented Evaluation
Proceedings of the IEEE International Test Conference on Test and Design Validity
Optimal Scan for Pipelined Testing: An Asynchronous Foundation
Proceedings of the IEEE International Test Conference on Test and Design Validity
Linear Test Times for Delay-Insensitive Circuits: a Compilation Strategy
Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies
Critical hazard free test generation for asynchronous circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A partial scan methodology for testing self-timed circuits
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Testing macro-module-based self-timed circuits
Testing macro-module-based self-timed circuits
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This paper presents a Design for Testability (DFT) toolcalled ACT (Asynchronous Circuit Testing) which uses apartial scan technique to make macro-module based self-timedcircuits testable. The ACT tool is the first of its kindfor testing macro-module based self-timed circuits. ACTmodifies designs automatically to incorporate partial scanand provides a complete path from schematic capture tophysical layout. It also has a test generation system to generatevectors for the testable design and to compute faultcoverage of the generated tests. The test generation systemincludes a module for doing critical hazard free test generationusing a new 6-valued algebra. ACT has been builtaround commercial tools from Viewlogic and Cascade. AViewlogic schematic is used as the design entry point andCascade tools are used for technology mapping.