Communications of the ACM
An introduction to modal and temporal logics for CCS
Proceedings of the UK/Japan workshop on Concurrency : theory, language, and architecture: theory, language, and architecture
The temporal logic of reactive and concurrent systems
The temporal logic of reactive and concurrent systems
Translating concurrent communicating programs into asynchronous circuits
Translating concurrent communicating programs into asynchronous circuits
Amulet1: Specification and verification in CCS
Amulet1: Specification and verification in CCS
VLSI RISC Architecture and Organization
VLSI RISC Architecture and Organization
Asynchronous Digital Circuit Design
Asynchronous Digital Circuit Design
VLSI '93 Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration
Practical verification and synthesis of low latency asynchronous systems
Practical verification and synthesis of low latency asynchronous systems
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We describe work completed on the specification and verification of the address interface of AMULET1, an industrial strength asynchronous microprocessor designed, fabricated and tested by Manchester University. AMULET1 is an asynchronous version of ARM, the best selling RISC chip in the 1980's, and now a leading macro-cell. The address interface is a substantial floor plan element, shared by several processes, which acts as a filter into memory for pc-values, memory swap, and single and multiple load/store operations. The specification is at the register transfer level and is sufficiently detailed to detect the known deadlocks in earlier designs and verify that the final version is deadlock free. The specification work was carried out in Milner's Calculus of Communicating Systems (CCS) and property checked using the ConcurrencyWorkbench (CWB). The work described is post facto--it was started after the AMULET1 chip had been sent for fabrication.