Communicating sequential processes
Communicating sequential processes
Designing regular array architectures using higher order functions
Proc. of a conference on Functional programming languages and computer architecture
ACM Transactions on Programming Languages and Systems (TOPLAS)
An interpreter for LOTOS, a specification language for distributed systems
Software—Practice & Experience
Q-Modules: Internally Clocked Delay-Insensitive Modules
IEEE Transactions on Computers
Translating programs into delay-insensitive circuits
Translating programs into delay-insensitive circuits
A simple approach to specifying concurrent systems
Communications of the ACM
Communication and concurrency
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
The design of an asynchronous microprocessor
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Developments in concurrency and communication
SHILPA: a high-level synthesis system for self-timed circuits
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
CML: A higher concurrent language
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Compiling with continuations
Translating concurrent communicating programs into asynchronous circuits
Translating concurrent communicating programs into asynchronous circuits
Verification of sequential and concurrent programs (2nd ed.)
Verification of sequential and concurrent programs (2nd ed.)
Symbolic Model Checking
Synthesis of Digital Design from Recursive Equations
Synthesis of Digital Design from Recursive Equations
Digital Design with VERILOG HDL
Digital Design with VERILOG HDL
The VERILOG Hardware Description Language
The VERILOG Hardware Description Language
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
IEEE Software
Formal Verification of a Pipelined Microprocessor
IEEE Software
Proceedings of the Functional Programming Languages and Computer Architecture
HardwareC -- A Language for Hardware Design (Version 2.0)
HardwareC -- A Language for Hardware Design (Version 2.0)
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Control-intensive IC's pose a significant challenge to the users of formal methods in designing hardware. These IC's have to support a wide variety of requirements including synchronous and asynchronous operations, polling and interrupt driven modes of operation, multiple concurrent threads of execution, nontrivial computational requirements, and programmability. We illustrate the use of formal methods in the design of a control-intensive IC called the "Intel 8251" Universal Synchronous/Asynchronous Receiver/Transmitter (USART), using our hardware description language "hopCP". A feature of hopCP is that it supports communication via asynchronous ports in addition to synchronous message passing. Asynchronous ports are distributed shared variables writable by exactly one process. We show the usefulness of this combination of communication constructs. We outline algorithms to determine safe usages of asynchronous ports, and also to discover other static properties of the specification. We discuss a compiled-code concurrent functional simulator called CFSIM, as well as the use of concurrent testers for driving CFSIM. The use of a semantically well-specified and simple language, and the associated analysis/simulation tools helps conquer the complexity of specifying and validating control-intensive IC's.