Using metro-on-chip in physical design flow for congestion and routability improvement
Microelectronics Journal
Asynchronous current mode serial communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Congestion and track usage improvement of large FPGAs using metro-on-FPGA methodology
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Integration, the VLSI Journal
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Surfing is a latchless pipelining technique where the propagation delays of gates and other logic functions are modulated to produce event attractors. We describe a test chip that demonstrates a surfing pipeline ring and then introduce new circuits that dramatically reduce the energy overhead for surfing. Our test chip implements a twelve-stage, surfing ring that supports two independent waves of computation without latches or other storage elements. We have operated the chip for over 48 hours and more than 2.6 * 10鹿驴 surfing events without an error. However, the energy consumption of the ring is unacceptable for scaling to larger applications. Thus, we introduce a new family of surfing circuits that use less energy than their domino counterparts and provide a factor of up to 1.75 improvement by the Et虏 metric. We demonstrate this new family with the design of a carry lookahead adder.