A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency

Authors:
Peter Caputa;Christer Svensson
Affiliations:
Linköping University;Linköping University
Venue:
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Year:
2006

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Abstract

We successfully show the practical feasibility of a purely electrical global on-chip communication link with near velocity-of-light delay. The implemented high-speed link comprises a 5mm long, fully shielded, repeaterless, on-chip global bus reaching 3Gb/s/wire in a standard 0.18 µm CMOS process. Transmission-line-styleinterconnects are achieved by routing signal wires in the thicker top metal M6 layer and utilizing a metal M4 ground return plane to realize near velocity-of-lightdata transmission. The nominal wire delay is measured to 52.8ps corresponding to 32% of the velocity of light in vacuum. A 22% measured worst-case crosstalk induced delay variation is dominated by inductive coupling.