Synchronous Full-Scan for Asynchronous Handshake Circuits
Journal of Electronic Testing: Theory and Applications
Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook
IEEE Design & Test
Initialization-based test pattern generation for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A synchronous mode as well as a scan mode of operation are added to a large class of asynchronous circuits, in compliance with LSSD design rules. This enables the application of mainstream tools for design-for-testability and test-pattern generation to asynchronous circuits. The approach is based on a systematic transformation of all single-output sequential gates into synchronous and scannable versions. By exploiting dynamic circuit operation in scan mode, the overhead of this transformation in terms of both circuit cost and circuit delay is kept minimal.