Synchronous Full-Scan for Asynchronous Handshake Circuits

  • Authors:
  • Frank Te Beest;Ad Peeters;Kees Van Berkel;Hans Kerkhoff

  • Affiliations:
  • MESA + Research Institute, University of Twente, Testable Design and Test of Microsystems, P.O. Box 217, 7500 AE Enschede, The Netherlands. F.J.teBeest@el.utwente.nl;Philips Research Laboratories, Electronic Design & Tools, Prof. Holstlaan 4, M/S WAY-31, 5656 AA Eindhoven, The Netherlands. Ad.Peeters@philips.com;Philips Research Laboratories, Information and Software Technology, Prof. Holstlaan 4, M/S WDC-31, 5656 AA Eindhoven, The Netherlands. Kees.van.Berkel@philips.com;MESA + Research Institute, University of Twente, Testable Design and Test of Microsystems, P.O. Box 217, 7500 AE Enschede, The Netherlands. H.G.Kerkhoff@el.utwente.nl

  • Venue:
  • Journal of Electronic Testing: Theory and Applications
  • Year:
  • 2003

Quantified Score

Hi-index 0.00

Visualization

Abstract

Handshake circuits form a special class of asynchronous circuits that has enabled the industrial exploitation of the asynchronous potential such as low power, low electromagnetic emission, and increased cryptographic security. In this paper we present a test solution for handshake circuits that brings synchronous test-quality to asynchronous circuits. We add a synchronous mode of operation to handshake circuits that allows full controllability and observability during test. This technique is demonstrated on some industrial examples and gives over 99% stuck-at fault coverage, using test-pattern generators developed for synchronous circuits. The paper describes how such a full-scan mode can be achieved, including an approach to minimize the number of dummy latches in case latches are used in the data path of the handshake circuit.