Adding Synchronous and LSSD Modes to Asynchronous Circuits
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents 3\phiLSSD, a novel, easily-automatable approach for scan insertion and ATPG of asynchronous circuits. 3\phiLSSD inserts scan latches only into global circuit feedback paths, leaving the local feedback paths of asynchronous state-storing gates intact. By employing a three-phase LSSD clocking scheme and complemented by a novel ATPG method, our approach achieves industrial quality testability with significantly less area overhead testing the same number of faults compared to full-scan LSSD. The effectiveness of our approach is demonstrated on an asynchronous SOC interconnection fabric, where our 3\phiLSSD ATPG tool achieved over 99% test coverage.