Synchronizing Large VLSI Processor Arrays
IEEE Transactions on Computers
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Practical Design of Globally-Asynchronous Locally-Synchronous Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Point to Point GALS Interconnect
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Evaluation of pausible clocking for interfacing high speed IP cores in GALS Framework
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Timing closure through a globally synchronous, timing partitioned design methodology
Proceedings of the 41st annual Design Automation Conference
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Demystifying Data-Driven and Pausible Clocking Schemes
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
StarSync: An extendable standard-cell mesochronous synchronizer
Integration, the VLSI Journal
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High-performance clocking of intellectual property (IP) modules, within a skew budget, is becoming difficult in deep sub-micron technologies. In this work, we propose a novel and all-digital synchronous design method for point-to-point communications, using two stages of interfacing registers and locally delayed clock with phase adjustments. This design is free from synchronizers and clock-data mismatch problems. Moreover, communicating modules run at frequencies which are virtually independent of the clock skew. We also provide a comprehensive case-wise mathematical analysis to facilitate design automation for synthesizing such designs as standard cells. An overall improvement in skew tolerance of up to n times (where n is the number of registers used), when compared to conventional designs, is achieved when the skew orientation is known and n/2 times if the skew orientation is unknown. Improvement in skew tolerance is validated using gate level simulations with the 0.18@mm TSMC CMOS technology. A prototype implementation of the proposed design using a Virtex-II Pro FPGA from Xilinx validates the claim that such designs allow a fast module to communicate with a slow module without constraining their frequencies.