Digital systems engineering
TNet: A Reliable System Area Network
IEEE Micro
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Timing Measurements of Synchronization Circuits
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A predictive synchronizer for periodic clock domains
Formal Methods in System Design
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip
IEEE Transactions on Computers
LIME: A Low-latency and Low-complexity On-chip Mesochronous Link with Integrated Flow Control
DSD '08 Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
Two-phase synchronization with sub-cycle latency
Integration, the VLSI Journal
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
The Even/Odd Synchronizer: A Fast, All-Digital, Periodic Synchronizer
ASYNC '10 Proceedings of the 2010 IEEE Symposium on Asynchronous Circuits and Systems
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
Low-Latency and Low-Overhead Mesochronous and Plesiochronous Synchronizers
DSD '11 Proceedings of the 2011 14th Euromicro Conference on Digital System Design
Synchronization in digital system design
IEEE Journal on Selected Areas in Communications
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StarSync, a mesochronous synchronizer, enables low latency and full throughput crossing of clock domain boundaries having same frequency but different phases. Full back pressure is supported, where the receiver can start and stop accepting words without any data loss. Variable depth buffering is provided, supporting a wide range of short and long range communications and accommodating multi-cycle wire delays. Burst data can also be accommodated thanks to buffering. Dynamic phase shifting due to varying voltage and temperature are mitigated by increasing the separation between write and read pointers. The synchronizer is exposed to metastability risk only during reset. It is suitable for implementation using standard cell design and requires neither delay lines nor other full custom circuits. It is shown that a minimum of four buffer stages are required, to mitigate skew in reset synchronization, in contrast with previous proposals for three stages.