Interface Design for Rationally Clocked GALS Systems

Authors:
Joycee Mekie;Supratik Chakraborty;D. K. Sharma;Girish Venkataramani;P. S. Thiagarajan
Affiliations:
Indian Institute of Technology, Bombay;Indian Institute of Technology, Bombay;Indian Institute of Technology, Bombay;Carnegie Mellon University;National University of Singapore
Venue:
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Year:
2006

Citing 0
Cited 6

Reasoning about synchronization in GALS systems

Formal Methods in System Design
Two efficient synchronous ↔ asynchronous converters well-suited for networks-on-chip in GALS architectures

Integration, the VLSI Journal
A Survey and Taxonomy of GALS Design Styles

IEEE Design & Test
A flexible communication scheme for rationally-related clock frequencies

ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Time aware modelling and analysis of multiclocked VLSI systems

ICFEM'06 Proceedings of the 8th international conference on Formal Methods and Software Engineering
Two efficient synchronous ↔ asynchronous converters well-suited for network on chip in GALS architectures

PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation

Quantified Score

Hi-index	0.00

Visualization

Abstract

We investigate the problem of designing interface circuits for rationally clocked modules in GALS systems. As a key contribution, we show that knowledge of flow-control protocols can be used to significantly optimize synchronization mechanisms. We present delayaugmented netcharts as a formalism for representing communication protocols and describe techniques to analyze them. We use the results of our analysis to design a simple yet generic interface that is optimized for the given protocol and is free from synchronization failures. We show by means of case studies the inherent advantages of our methodology over an existing solution technique.