DATE '00 Proceedings of the conference on Design, automation and test in Europe
Timing analysis of asynchronous circuits using timed automata
CHARME '95 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Formal Verification of Safety Properties in Timed Circuits
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Verification of timed circuits with symbolic delays
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Verification of Concurrent Systems with Parametric Delays Using Octahedra
ACSD '05 Proceedings of the Fifth International Conference on Application of Concurrency to System Design
Timed circuit verification using TEL structures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timed verification of the generic architecture of a memory circuit using parametric timed automata
Formal Methods in System Design
Verification of the generic architecture of a memory circuit using parametric timed automata
FORMATS'06 Proceedings of the 4th international conference on Formal Modeling and Analysis of Timed Systems
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This paper proposes a high-level formalism, called Abstract Functional and Timing Graph (AFTG), for describing a memory architecture, which combines logical functionality and timing. After translation of the AFTG into the form a timed automaton, we are able to compute the response times of the modeled memory, and check their consistency with the values specified in the datasheet. We also address the problem of finding optimal values of setup timings.