Theoretical Computer Science
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
TACAS '95 Proceedings of the First International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Timing analysis of asynchronous circuits using timed automata
CHARME '95 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Timing Assumptions and Verification of Finite-State Concurrent Systems
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Delay Analysis in Synchronous Programs
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Verification of timed circuits with symbolic delays
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Timing analysis of an embedded memory: SPSMALL
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
Time Separation of Events: An Inverse Method
Electronic Notes in Theoretical Computer Science (ENTCS)
IMITATOR: A Tool for Synthesizing Constraints on Timing Bounds of Timed Automata
ICTAC '09 Proceedings of the 6th International Colloquium on Theoretical Aspects of Computing
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Using a variant of Clariso-Cortadella’s parametric method for verifying asynchronous circuits, we formally derive a set of linear constraints that ensure the correctness of some crucial timing behaviours of the architecture of SPSMALL memory. This allows us to check two different implementations of this architecture.