Compiling Real-Time Specifications into Extended Automata
IEEE Transactions on Software Engineering - Special issue: specification and analysis of real-time systems
Parametric real-time reasoning
STOC '93 Proceedings of the twenty-fifth annual ACM symposium on Theory of computing
Theoretical Computer Science
TACAS '95 Proceedings of the First International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Linear Parametric Model Checking of Timed Automata
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Symbolic Parametric Safety Analysis of Linear Hybrid Systems with BDD-Like Data-Structures
IEEE Transactions on Software Engineering
A Counterexample-Guided Approach to Parameter Synthesis for Linear Hybrid Automata
HSCC '08 Proceedings of the 11th international workshop on Hybrid Systems: Computation and Control
Verification of the generic architecture of a memory circuit using parametric timed automata
FORMATS'06 Proceedings of the 4th international conference on Formal Modeling and Analysis of Timed Systems
Behavioral cartography of timed automata
RP'10 Proceedings of the 4th international conference on Reachability problems
Parametric verification and test coverage for hybrid automata using the inverse method
RP'11 Proceedings of the 5th international conference on Reachability problems
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We present here Imitator , a tool for synthesizing constraints on timing bounds (seen as parameters) in the framework of timed automata. Unlike classical synthesis methods, we take advantage of a given reference valuation of the parameters for which the system is known to behave properly. Our aim is to generate a constraint such that, under any valuation satisfying this constraint, the system is guaranteed to behave, in terms of alternating sequences of locations and actions, as under the reference valuation. This is useful for safely relaxing some values of the reference valuation, and optimizing timing bounds of the system. We have successfully applied our tool to various examples of asynchronous circuits and protocols.