Parametric real-time reasoning
STOC '93 Proceedings of the twenty-fifth annual ACM symposium on Theory of computing
Finite transition systems: semantics of communicating systems
Finite transition systems: semantics of communicating systems
Theoretical Computer Science
The algorithmic analysis of hybrid systems
Theoretical Computer Science - Special issue on hybrid systems
Verification of Real-Time Systems using Linear Relation Analysis
Formal Methods in System Design - Special issue on computer aided verification (CAV 93)
Symbolic timing verification of timing diagrams using Presburger formulas
DAC '97 Proceedings of the 34th annual Design Automation Conference
Timed circuits: a new paradigm for high-speed design
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Automatic discovery of linear restraints among variables of a program
POPL '78 Proceedings of the 5th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Timing Assumptions and Verification of Finite-State Concurrent Systems
Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems
Symbolic Techniques for Parametric Reasoning about Counter and Clock Systems
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Automatic Derivation of Timing Constraints by Failure Analysis
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Proceedings of the Real-Time: Theory in Practice, REX Workshop
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Formal Verification of Safety Properties in Timed Circuits
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
WCRE '01 Proceedings of the Eighth Working Conference on Reverse Engineering (WCRE'01)
Verification of timed circuits with symbolic delays
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
The octahedron abstract domain
Science of Computer Programming
Scalable analysis of linear systems using mathematical programming
VMCAI'05 Proceedings of the 6th international conference on Verification, Model Checking, and Abstract Interpretation
Timed circuit verification using TEL structures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A technique for the verification of concurrent parametric timed systems is presented. In the systems under study, each action has a bounded delay where the bounds are either constants or parameters. Given a safety property, the analysis computes automatically a set of constraints on the parameters that is sufficient to guarantee the property. The main contribution is an innovative representation of the parametric timed state space based on bit-vectors. Experimental results from the domain of timed circuits show that this representation improves the efficiency of the verification significantly with a small impact on the accuracy of the derived constraints.