Efficient Verification of Timed Automata Using Dense and Discrete Time Semantics
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Verification of Speed-Dependences in Single-Rail Handshake Circuits
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Timed Trace Theoretic Verification Using Partial Order Reduction
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Formal Verification of Safety Properties in Timed Circuits
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Relative Timing Based Verification of Timed Circuits and Systems
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Partial order reduction for verification of timed systems
Partial order reduction for verification of timed systems
Verification of timed circuits with symbolic delays
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Verification of Concurrent Systems with Parametric Delays Using Octahedra
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
An Inverse Method for Parametric Timed Automata
Electronic Notes in Theoretical Computer Science (ENTCS)
Full simulation coverage for SystemC transaction-level models of systems-on-a-chip
Formal Methods in System Design
Test coverage for loose timing annotations
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
Synthesis of timing parameters satisfying safety properties
RP'11 Proceedings of the 5th international conference on Reachability problems
Verification of Concurrent Systems with Parametric Delays Using Octahedra
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
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This work proposes a technique to automatically obtain timing constraints for a given timed circuit to operate correctly. A designated set of delay parameters of a circuit are first set to sufficiently large bounds, and verification runs followed by failure analysis are repeated. Each verification run performs timed state space enumeration under the given delay bounds, and produces a failure trace if it exists. The failure trace is analyzed, and sufficient timing constraints to prevent the failure is obtained. Then, the delay bounds are tightened according to the timing constraints by using an ILP (Integer Linear Programming) solver. This process terminates when either some delay bounds under which no failure is detected are found or no new delay bounds to prevent the failures can be obtained. The experimental results using a naive implementation show that the proposed method can efficiently handle asynchronous benchmark circuits and nontrivial GasP circuits.