Automatic Derivation of Timing Constraints by Failure Analysis
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Congestion and Starvation Detection in Ripple FIFOs
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a method for designing a special type of asynchronous circuits, called GasP circuits, and illustrates the method by a novel design of a low-latency, high-throughput FIFO, called a Square FIFO. The design method includes a graphical notation that permits the specification not only of circuit topology but also of the time separation between any two succeeding events. A Square FIFO test chip has been fabricated in a 0.35µ CMOS process through MOSIS. Test results show that the Square FIFO chip can sustain a maximum throughput of 1.56 Giga Data Items per second for a large range of occupancies.