Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace algebra for automatic verification of real-time concurrent systems
Trace algebra for automatic verification of real-time concurrent systems
Verification of asynchronous interface circuits with bounded wire delays
Journal of VLSI Signal Processing Systems - Special issue: asynchronous circuit design for VLSI signal processing
Analysis and identification of speed-independent circuits on an event model
Formal Methods in System Design - Special issue on designing correct circuits
Automatic gate-level synthesis of speed-independent circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications
Automatic Abstraction for Verification of Timed Circuits and Systems
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Hazard Checking of Timed Asynchronous Circuits Revisited
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
A Conservative Framework for Safety-Failure Checking
IEICE - Transactions on Information and Systems
Hazard Checking of Timed Asynchronous Circuits Revisited
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
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