The first asynchronous microprocessor: the test results
ACM SIGARCH Computer Architecture News
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Symbolic model checking: an approach to the state explosion problem
Symbolic model checking: an approach to the state explosion problem
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
TITAC: Design of A Quasi-Delay-Insensitive Microprocessor
IEEE Design & Test
Petri Net Theory and the Modeling of Systems
Petri Net Theory and the Modeling of Systems
The Design and Evaluation of an Asynchronous Microprocessor
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets
Proceedings of the 16th International Conference on Application and Theory of Petri Nets
A Stubborn Attack On State Explosion
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Using Partial Orders to Improve Automatic Verification Methods
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Trace Theoretic Verification of Asynchronous Circuits Using Unfoldings
Proceedings of the 7th International Conference on Computer Aided Verification
Conformance and mirroring for timed asychronous circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Verification of Bounded Delay Asynchronous Circuits with Timed Traces
AMAST '98 Proceedings of the 7th International Conference on Algebraic Methodology and Software Technology
Timed Trace Theoretic Verification Using Partial Order Reduction
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Automated interface refinement for compositional verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Compositional reachability analysis for efficient modular verification of asynchronous designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A compositional minimization approach for large asynchronous design verification
SPIN'12 Proceedings of the 19th international conference on Model Checking Software
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In this paper, we propose a method to generate the reduced state spaces in which the trace theoretic verification method of asynchronous circuits works correctly and efficiently. The state space reduction is based on the stubborn set method and similar ideas, but they have been extended so that the conformance checking works correctly in the reduced state space. Our state reduction algorithm also guarantees that a kind of simple liveness properties are correctly checked. Some experimental results show the efficiency of the proposed method.