Theoretical Computer Science
Symbolic model checking for real-time systems
Information and Computation
Journal of the ACM (JACM)
Model Checking of Real-Time Reachability Properties Using Abstractions
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
Compositional Specification of Timed Systems (Extended Abstract)
STACS '96 Proceedings of the 13th Annual Symposium on Theoretical Aspects of Computer Science
Timing analysis of asynchronous circuits using timed automata
CHARME '95 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
IF-2.0: A Validation Environment for Component-Based Real-Time Systems
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Real time temporal logic: past, present, future
FORMATS'05 Proceedings of the Third international conference on Formal Modeling and Analysis of Timed Systems
Modular verification of timed circuits using automatic abstraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume and Entropy of Regular Timed Languages: Discretization Approach
CONCUR 2009 Proceedings of the 20th International Conference on Concurrency Theory
Volume and Entropy of Regular Timed Languages: Analytic Approach
FORMATS '09 Proceedings of the 7th International Conference on Formal Modeling and Analysis of Timed Systems
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Hi-index | 0.00 |
We develop a new technique for generating small-complexity abstractions of timed automata that provide an approximation of their timed input-output behavior. This abstraction is obtained by first augmenting the automaton with additional input clocks, computing the "reachable" timed automaton that corresponds to the augmented model and finally "hiding" the internal variables and clocks of the system. As a result we obtain a timed automaton that does not allow any qualitative behavior which is infeasible due to timing constraints, and which maintains a relaxed form of the timing constraints associated with the feasible behaviors. We have implemented this technique and applied it to several examples from different application domains.